1. Field of the Invention
The present invention relates to analog-digital coders and, in particular, to coders conforming to the compression laws A and .mu. defined in the standards of the CCITT (International Telegraph and Telephone Consultative Committee).
2. Description of the Prior Art
In order to code an analog signal in a series of bits, conventional coders generally effect the sequential operations of sampling the analog signal, quantifying and coding the sample in binary form. The coding establishes a one-to-one correspondence between the values quantified and their expression in binary form. Generally speaking, the conversion time of such devices is proportional to the sum of the sequential operations mentioned above. The times corresponding to the operations of quantifying and coding the samples signal increase as the complexity of the circuits enabling their execution increase.
These coders have been improved by means of charge transfer devices (hereinafter CTD) which enable the sampling operation to be effected better and more rapidly (elimination of a capacitor used as a memory), thus improving the conversion time.
The known solution is to use coders of the pulse type or successive approximation type (trial and error).
However, pulse coders require CTD's with a very large number of electrodes, this number limiting the conversion speed. They also require a very rapid comparator, with a very low threshold voltage and high dynamic performance; such a comparator is difficult to design. In the case of successive approximation coders, it is necessary, for each bit tested, to record it in the CTD and then to erase it, which also has the disadvantage of limiting conversion time (even if there are fewer electrodes than the minimum required for coders). Furthermore, the structure is still complex.
Analog-digital coders of the serial type are also known wherein coding is based on successive comparisons of the voltage to be coded in relation to fractions of a reference voltage, each successive comparison furnishing a bit corresponding to the analog voltage for coding, from the most significant bit to the least significant bit. Among others these different operations necessitate the use of multipliers as well as the storage of the results. These simply structured coders use capacitors for storing the results, which limits the conversion speed (owing to the time constant for charging and discharging the capacitors) as well as precision (since the leakage of the capacitors is not negligible with relatively long storage times).